/*  File name: C5510.h


    14Dec2007 .. initial version .. KMetzger

*/

#ifndef C5510h

#define C5510h

// Clock Generator Register

#define CLKMD  *((ioport unsigned *)0x1C00)

// Timer definitions

#define TIM0   *((ioport unsigned *)0x1000)
#define PRD0   *((ioport unsigned *)0x1001)
#define TCR0   *((ioport unsigned *)0x1002)
#define PRSC0  *((ioport unsigned *)0x1003)

#define TIM1   *((ioport unsigned *)0x2400)
#define PRD1   *((ioport unsigned *)0x2401)
#define TCR1   *((ioport unsigned *)0x2402)
#define PRSC1  *((ioport unsigned *)0x2403)


// McBSP definitions

#define DRR2(port)  *((ioport unsigned *)(0x2800+port*0x0400))
#define DRR1(port)  *((ioport unsigned *)(0x2801+port*0x0400))
#define DXR2(port)  *((ioport unsigned *)(0x2802+port*0x0400))
#define DXR1(port)  *((ioport unsigned *)(0x2803+port*0x0400))
#define SPCR2(port) *((ioport unsigned *)(0x2804+port*0x0400))
#define SPCR1(port) *((ioport unsigned *)(0x2805+port*0x0400))
#define RCR2(port)  *((ioport unsigned *)(0x2806+port*0x0400))
#define RCR1(port)  *((ioport unsigned *)(0x2807+port*0x0400))
#define XCR2(port)  *((ioport unsigned *)(0x2808+port*0x0400))
#define XCR1(port)  *((ioport unsigned *)(0x2809+port*0x0400))
#define SRGR2(port) *((ioport unsigned *)(0x280A+port*0x0400))
#define SRGR1(port) *((ioport unsigned *)(0x280B+port*0x0400))
#define MCR2(port)  *((ioport unsigned *)(0x280C+port*0x0400))
#define MCR1(port)  *((ioport unsigned *)(0x280D+port*0x0400))
#define PCR(port)   *((ioport unsigned *)(0x2812+port*0x0400))

// Alternate McBSP definitions

#define DRR20  *((ioport unsigned *)0x2800)
#define DRR10  *((ioport unsigned *)0x2801)
#define DXR20  *((ioport unsigned *)0x2802)
#define DXR10  *((ioport unsigned *)0x2803)
#define SPCR20 *((ioport unsigned *)0x2804)
#define SPCR10 *((ioport unsigned *)0x2805)
#define RCR20  *((ioport unsigned *)0x2806)
#define RCR10  *((ioport unsigned *)0x2807)
#define XCR20  *((ioport unsigned *)0x2808)
#define XCR10  *((ioport unsigned *)0x2809)
#define SRGR20 *((ioport unsigned *)0x280A)
#define SRGR10 *((ioport unsigned *)0x280B)
#define MCR20  *((ioport unsigned *)0x280C)
#define MCR10  *((ioport unsigned *)0x280D)
#define PCR0   *((ioport unsigned *)0x2812)

#define DRR21  *((ioport unsigned *)0x2C00)
#define DRR11  *((ioport unsigned *)0x2C01)
#define DXR21  *((ioport unsigned *)0x2C02)
#define DXR11  *((ioport unsigned *)0x2C03)
#define SPCR21 *((ioport unsigned *)0x2C04)
#define SPCR11 *((ioport unsigned *)0x2C05)
#define RCR21  *((ioport unsigned *)0x2C06)
#define RCR11  *((ioport unsigned *)0x2C07)
#define XCR21  *((ioport unsigned *)0x2C08)
#define XCR11  *((ioport unsigned *)0x2C09)
#define SRGR21 *((ioport unsigned *)0x2C0A)
#define SRGR11 *((ioport unsigned *)0x2C0B)
#define MCR21  *((ioport unsigned *)0x2C0C)
#define MCR11  *((ioport unsigned *)0x2C0D)
#define PCR1   *((ioport unsigned *)0x2C12)

#define DRR22  *((ioport unsigned *)0x3000)
#define DRR12  *((ioport unsigned *)0x3001)
#define DXR22  *((ioport unsigned *)0x3002)
#define DXR12  *((ioport unsigned *)0x3003)
#define SPCR22 *((ioport unsigned *)0x3004)
#define SPCR12 *((ioport unsigned *)0x3005)
#define RCR22  *((ioport unsigned *)0x3006)
#define RCR12  *((ioport unsigned *)0x3007)
#define XCR22  *((ioport unsigned *)0x3008)
#define XCR12  *((ioport unsigned *)0x3009)
#define SRGR22 *((ioport unsigned *)0x300A)
#define SRGR12 *((ioport unsigned *)0x300B)
#define MCR22  *((ioport unsigned *)0x300C)
#define MCR12  *((ioport unsigned *)0x300D)
#define PCR2   *((ioport unsigned *)0x3012)


// memory mapped registers for FarPeek/FarPoke access

#define IER0 ((unsigned long)0x00)
#define IFR0 ((unsigned long)0x01)
#define IER1 ((unsigned long)0x45)
#define IFR1 ((unsigned long)0x46)
#define IVPD ((unsigned long)0x49)
#define IVPH ((unsigned long)0x4A)

// interrupt related bit definitions

#define RINT0 (0x28>>1)
#define RINT0_BIT 0x0020
#define XINT0 (0x88>>1)
#define XINT0_BIT 0x0002

#define RINT1 (0x30>>1)
#define RINT1_BIT 0x0040
#define XINT1 (0x38>>1)
#define XINT1_BIT 0x0080

#define RINT2 (0x60>>1)
#define RINT2_BIT 0x1000
#define XINT2 (0x68>>1)
#define XINT2_BIT 0x2000

// define bit fields for timer TCR

#define  T_IDLEEN 0x8000
#define  T_INTEX  0x4000
#define  T_ERRTM  0x2000
#define  T_FUNC   0x0800
#define  T_TLB    0x0400
#define  T_SOFT   0x0200
#define  T_FREE   0x0100
#define  T_PWD    0x0040
#define  T_ARB    0x0020
#define  T_TSS    0x0010
#define  T_CP     0x0004
#define  T_POLAR  0x0002
#define  T_DATOUT 0x0001


#endif

